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global declarations illegal in verilog 2001 syntax Task

I've got a verilog file which all I want to have in it is a task that does some maths which I am then include "maths.v" in another file and calling the task by writing mathsfunction; in a initial begin - end block in the other file which should run the task at that point if I understand correctly, the code is below:

Maths.v

task mathsfunction;
reg [0:31]   x;
reg [0:31]   y;
reg [0:31]   z;
begin
    x = $urandom;
    y = $urandom;
    z = x + y
end
#200    
endtask

I'm getting one compile error which is on the first line task mathsfunction; which is Global declarations are illegal in Verilog 2001 syntax. From what I've learnt so far, having a verilog file which is just a task (not a module, I dont want it to be a module) should be fine? So not sure why this doesn't work.

Any help would be great

1个回答

    最佳答案
  1. Your first problem is that you're confusing Verilog2K ("Verilog") and SystemVerilog. In Verilog, task declarations can only appear inside modules or generates (and not 'globally'), which gives your error message. Second, your task contains two statements (the begin/end seq block and the timing control), which is not valid in Verilog; SV relaxes this. Having said that, putting the #200 outside the block serves no purpose, so you might as well move it inside the block to make it Verilog-compatible.

    Your next problem is that your task has no inputs or outputs - x, y, z are internal; you need to make them input, output, or inout.

    Finally, you've cut/pasted incorrectly - this code won't compile without a couple more semicolons.